Table 35. Analog Watchdog Comparison; Figure 36. Analog Watchdog Guarded Area - STMicroelectronics STM32F05 series Reference Manual

Analog-to-digital converter (ADC)
The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is
below a lower threshold or above a higher threshold. These thresholds are programmed in
the 12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can
be enabled by setting the AWDIE bit in the ADC_IER register.
The AWD flag is cleared by software by writing 1 to it.
When converting a data with a resolution of less than 12-bit (according to bits DRES[1:0]),
the LSB of the programmed thresholds must be kept cleared because the internal
comparison is always performed on the full 12-bit raw converted data (left aligned).
Table 35
Table 35. Analog watchdog comparison
Analog Watchdog comparison between:
Resolutio
n
Raw converted
bits
data, left
RES[1:0]
aligned
00: 12-bit DATA[11:0]
01: 10-bit DATA[11:2],00
10: 8-bit DATA[11:4],0000
11: 6-bit DATA[11:6],000000
1. The watchdog comparison is performed on the raw converted data before any alignment calculation.
Table 36
register to enable the analog watchdog on one or more channels.

Figure 36. Analog watchdog guarded area

Table 36.
Channels guarded by the analog watchdog
None
All channels
(1)
Single
1. Selected by the AWDCH[4:0] bits
188/742
describes how the comparison is performed for all the possible resolutions.
Thresholds
(1)
LT[11:0] and HT[11:0]
LT[11:0] and HT[11:0]
LT[11:0] and HT[11:0]
LT[11:0] and HT[11:0]
shows how to configure the AWDSGL and AWDEN bits in the ADC_CFGR1
Analog voltage
Higher threshold
Lower threshold
Analog watchdog channel selection
channel
Doc ID 018940 Rev 1
Comments
-
The user must configure LT1[1:0] and HT1[1:0] to "00"
The user must configure LT1[3:0] and HT1[3:0] to
"0000"
The user must configure LT1[5:0] and HT1[5:0] to
"000000"
Guarde d area
AWDSGL bit
x
0
1
RM0091
HTR
LTR
ai16048
AWDEN bit
0
1
1