Control Register 2 (I2Cx_Cr2) - STMicroelectronics STM32F05 series Reference Manual

Inter-integrated circuit (I
23.7.2

Control register 2 (I2Cx_CR2)

Address offset: 0x04
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
HEAD
NACK STOP START
rs rs rs
Bits 31:27 Reserved, must be kept at reset value.
Bit 26 PECBYTE: Packet error checking byte
Note: Writing '0' to this bit has no effect.
Bit 25 AUTOEND: Automatic end mode (master mode)
Note: This bit has no effect in slave mode or when the RELOAD bit is set.
Bit 24 RELOAD: NBYTES reload mode
Bits 23:16 NBYTES[7:0]: Number of bytes
Note: Changing these bits when the START bit is set is not allowed.
522/742
2
C) interface
28 27 26 25
PEC
AUTO
Res.
END
BYTE
rs rw
12 11 10 9
RD_W
ADD10
10R RN
rw rw rw
This bit is set by software, and cleared by hardware when the PEC is transferred, or
when a STOP condition or an Address Matched is received, also when PE=0 or
SWRST is set.
0: No PEC transfer.
1: PEC transmission/reception is requested
This bit has no effect when RELOAD is set.
This bit has no effect is slave mode when SBC=0.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
Please refer to Section 23.3: I2C
This bit is set and cleared by software.
0: software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low.
1: Automatic end mode: a STOP condition is automatically sent when NBYTES data are
transferred.
This bit is set and cleared by software.
0: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow).
1: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded).
TCR flag is set when NBYTES data are transferred, stretching SCL low.
The number of bytes to be transmitted/received is programmed there. This field is don't care
in slave mode with SBC=0.
Doc ID 018940 Rev 1
24 23 22 21
RE
LOAD
rw
8 7 6 5
SADD[9:0]
implementation.
20 19 18
NBYTES[7:0]
rw
4 3 2
rw
RM0091
17 16
1 0