Figure 105. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr=0X6 - STMicroelectronics STM32F05 series Reference Manual

RM0091
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter continues counting up and down, based on the current auto-reload
value.
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupt when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
●
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
●
The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that if the update source is a counter overflow, the auto-
reload is updated before the counter is reloaded, so that the next period is the expected
one (the counter is loaded with the new value).
The following figures show some examples of the counter behavior for different clock
frequencies.

Figure 105. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6

1. Here, center-aligned mode 1 is used (for more details refer to
and TIM3_CR1) on page
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter underflow
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
329).
Doc ID 018940 Rev 1
General-purpose timers (TIM2 and TIM3)
04 03 02 01 00 01 02 03 04 05 06 05 04 03
Section 16.4.1: TIM2 and TIM3 control register 1 (TIM2_CR1
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