Apb2 Peripheral Reset Register (Rcc_Apb2Rstr) - STMicroelectronics STM32F05 series Reference Manual

RM0091
Bit 4 PLLRDYF: PLL ready interrupt flag
Bit 3 HSERDYF: HSE ready interrupt flag
Bit 2 HSIRDYF: HSI ready interrupt flag
Bit 1 LSERDYF: LSE ready interrupt flag
Bit 0 LSIRDYF: LSI ready interrupt flag
7.4.4

APB2 peripheral reset register (RCC_APB2RSTR)

Address offset: 0x0C
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
31 30 29 28
Res Res Res Res
15 14 13 12
USART1 SPI1
Res Res
RST RST
rw rw
Bits 31:23
Set by hardware when the PLL locks and PLLRDYDIE is set.
Cleared by software setting the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
Set by hardware when the HSE clock becomes stable and HSERDYDIE is set.
Cleared by software setting the HSERDYC bit.
0: No clock ready interrupt caused by the HSE oscillator
1: Clock ready interrupt caused by the HSE oscillator
Set by hardware when the HSI clock becomes stable and HSIRDYDIE is set in a response
to setting the HSION (refer to
but the HSI oscillator is enabled by the peripheral through a clock request, this bit is not set
and no interrupt is generated.
Cleared by software setting the HSIRDYC bit.
0: No clock ready interrupt caused by the HSI oscillator
1: Clock ready interrupt caused by the HSI oscillator
Set by hardware when the LSE clock becomes stable and LSERDYDIE is set.
Cleared by software setting the LSERDYC bit.
0: No clock ready interrupt caused by the LSE oscillator
1: Clock ready interrupt caused by the LSE oscillator
Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set.
Cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the LSI oscillator
1: Clock ready interrupt caused by the LSI oscillator
27 26 25
Res Res Res
11 10 9
TIM1 ADC
Res
RST RST
rw rw
Reserved, must be kept at reset value.
Doc ID 018940 Rev 1
Clock control register
24 23 22 21
DBG MCU
Res Res Res
RST
rw
8 7 6
Res Res Res Res
Reset and clock control (RCC)
(RCC_CR)). When HSION is not set
20 19 18
TIM17
Res Res
RST
rw
5 4 3 2
Res Res Res
17 16
TIM16
TIM15RST
RST
rw rw
1 0
SYSCFG
Res
COMPRST
rw
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