Dma Requests - STMicroelectronics STM32F05 series Reference Manual

Inter-integrated circuit (I
The ALERT flag is set when the I2C interface is configured as a Host (SMBHEN=1), the
alert pin detection is enabled (ALERTEN=1) and a falling edge is detected on the SMBA pin.
An interrupt is generated if the ERRIE bit is set in the I2Cx_CR1 register.
23.4.17

DMA requests

Transmission using DMA
DMA (Direct Memory Access) can be enabled for transmission by setting the TXDMAEN bit
in the I2Cx_CR1 register. Data is loaded from an SRAM area configured using the DMA
peripheral (see
I2Cx_TXDR register whenever the TXIS bit is set.
Only the data are transferred with DMA.
● In master mode: the initialization, the slave address, direction, number of bytes and
START bit are programmed by software (the transmitted slave address cannot be
transferred with DMA). When all data are transferred using DMA, the DMA must be
initialized before setting the START bit. The end of transfer is managed with the
NBYTES counter. Refer to
●
In slave mode:
–
–
●
For instances supporting SMBus: the PEC transfer is managed with NBYTES counter.
Refer to
page
Note: If DMA is used for transmission, the TXIE bit does not need to be enabled.
Reception using DMA
DMA (Direct Memory Access) can be enabled for reception by setting the RXDMAEN bit in
the I2Cx_CR1 register. Data is loaded from the I2Cx_RXDR register to an SRAM area
configured using the DMA peripheral (refer to
(DMA) on page
transferred with DMA.
● In master mode, the initialization, the slave address, direction, number of bytes and
START bit are programmed by software. When all data are transferred using DMA, the
DMA must be initialized before setting the START bit. The end of transfer is managed
with the NBYTES counter. Refer to
● In slave mode with NOSTRETCH=0, when all data are transferred using DMA, the
DMA must be initialized before the address match event, or in the ADDR interrupt
subroutine, before clearing the ADDR flag.
● If SMBus is supported (see
managed with the NBYTES counter. Refer
SMBus Master receiver on page
Note: If DMA is used for reception, the RXIE bit does not need to be enabled.
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C) interface
Section 10: Direct memory access controller (DMA) on page
With NOSTRETCH=0, when all data are transferred using DMA, the DMA must be
initialized before the address match event, or in ADDR interrupt subroutine, before
clearing ADDR.
With NOSTRETCH=1, the DMA must be initialized before the address match
event.
SMBus Slave transmitter on page 506
510.
142) whenever the RXNE bit is set. Only the data (including PEC) are
Doc ID 018940 Rev 1
Master transmitter on page
and
Section 10: Direct memory access controller
Master receiver on page
Section 23.3: I2C implementation): the PEC transfer is
toSMBus Slave receiver on page 508
512.
142) to the
491.
SMBus Master transmitter on
495.
RM0091
and