Universal Synchronous Asynchronous Receiver Transmitter (Usart); Usart Introduction; Usart Main Features - STMicroelectronics STM32F05 series Reference Manual

RM0091
25 Universal synchronous asynchronous receiver
transmitter (USART)
25.1

USART introduction

The universal synchronous asynchronous receiver transmitter (USART) offers a flexible
means of full-duplex data exchange with external equipment requiring an industry standard
NRZ asynchronous serial data format. The USART offers a very wide range of baud rates
using a baud rate generator.
It supports synchronous one-way communication and half-duplex single wire
communication. It also supports the LIN (local interconnection network), Smartcard Protocol
and IrDA (infrared data association) SIR ENDEC specifications, and modem operations
(CTS/RTS). It allows multiprocessor communication.
High speed data communication is possible by using the DMA for multibuffer configuration.
25.2

USART main features

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Full duplex, asynchronous communications
● NRZ standard format (mark/space)
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Configurable oversampling method by 16 or by 8 to give flexibility between speed and
clock tolerance
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Baud rate generator systems
–
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Dual clock domain allowing
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–
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Auto baud rate detection
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Programmable data word length (8 or 9 bits)
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Programmable data order with MSB-first or LSB-first shifting
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Configurable stop bits - support for 1 or 2 stop bits
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Synchronous mode and clock output for synchronous communication
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Single-wire half-duplex communication
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Continuous communication using DMA (direct memory access)
–
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Separate enable bits for transmitter and receiver
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Separate signal polarity control for transmission and reception
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Swappable Tx/Rx pin configuration
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Hardware flow control for modem and RS-485 transceiver
●
Transfer detection flags:
–
–
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Universal synchronous asynchronous receiver transmitter (USART)

A common programmable transmit and receive baud rate of up to 6 Mbit/s when
the clock frequency is 48 MHz and oversampling is by 8
UART functionality and wakeup from Stop mode
Convenient baud rate programming independent from the PCLK reprogramming
Buffering of received/transmitted bytes in reserved SRAM using centralized DMA
Receive buffer full
Transmit buffer empty
Busy and end of transmission flags
Doc ID 018940 Rev 1 571/742