Smbus: I2Cx_Timeoutr Register Configuration Examples - STMicroelectronics STM32F05 series Reference Manual

RM0091
Timeout detection
The timeout detection is enabled by setting the TIMOUTEN and TEXTEN bits in the
I2Cx_TIMEOUTR register. The timers must be programmed in such a way that they detect a
timeout before the maximum time given in the SMBus specification ver. 2.0.
● t
TIMEOUT
In order to enable the t
programmed with the timer reload value in order to check the t
TIDLE bit must be configured to '0' in order to detect the SCL low level timeout.
Then the timer is enabled by setting the TIMOUTEN in the I2Cx_TIMEOUTR register.
If SCL is tied low for a time greater than (TIMEOUTA+1) x 2048 x t
flag is set in the I2Cx_ISR register.
Refer to
Caution: Changing the TIMEOUTA[11:0] bits and TIDLE bit configuration is not allowed when the
TIMEOUTEN bit is set.
● t
LOW:SEXT
Depending on if the peripheral is configured as a master or as a slave, The 12-bit
TIMEOUTB timer must be configured in order to check t
t
LOW:MEXT
same value for the both.
Then the timer is enabled by setting the TEXTEN bit in the I2Cx_TIMEOUTR register.
If the SMBus peripheral performs a cumulative SCL stretch for a time greater than
(TIMEOUTB+1) x 2048 x t
detection on page 503
Refer to
Caution: Changing the TIMEOUTB configuration is not allowed when the TEXTEN bit is set.
Bus Idle detection
In order to enable the t
programmed with the timer reload value in order to obtain the t
TIDLE bit must be configured to '1 in order to detect both SCL and SDA high level
timeout.
Then the timer is enabled by setting the TIMOUTEN bit in the I2Cx_TIMEOUTR
register.
If both the SCL and SDA lines remain high for a time greater than (TIMEOUTA+1) x 4 x
t
I2CCLK
Refer to
Caution: Changing the TIMEOUTA and TIDLE configuration is not allowed when the TIMEOUTEN is
set.
SMBus:
23.4.13
This section is relevant only when SMBus feature is supported. Please refer to
I2C implementation.
●
Configuring the maximum duration of t
check
TIMEOUT
Table 72: Examples of TIMEOUTA settings for various I2CCLK frequencies
and t check
LOW:MEXT
for a master. As the standard specifies only a maximum, you can choose the
I2CCLK
section, the TIMEOUT flag is set in the I2Cx_ISR register.
Table 73: Examples of TIMEOUTB settings for various I2CCLK frequencies
check, the 12-bit TIMEOUTA[11:0] field must be
IDLE
, the TIMEOUT flag is set in the I2Cx_ISR register.
Table 74: Examples of TIMEOUTA settings for various I2CCLK frequencies
I2Cx_TIMEOUTR register configuration examples
Doc ID 018940 Rev 1
Inter-integrated circuit (I
check, the 12-bit TIMEOUTA[11:0] bits must be
, and in the timeout interval described in
to 25 ms:
TIMEOUT
2
C) interface
parameter. The
TIMEOUT
, the TIMEOUT
I2CCLK
for a slave and
LOW:SEXT
Bus idle
parameter. The
IDLE
Section 23.3:
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