Tsc Interrupt Status Register (Tsc_Isr); Tsc I/O Hysteresis Control Register (Tsc_Iohcr) - STMicroelectronics STM32F05 series Reference Manual

Touch sensing controller (TSC)
27.6.4

TSC interrupt status register (TSC_ISR)

Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 MCEF: Max count error flag
This bit is set by hardware as soon as an analog I/O group counter reaches the max count
value specified. It is cleared by software writing 1 to the bit MCEIC of the TSC_ICR register.
0: No max count error (MCE) detected
1: Max count error (MCE) detected
Bit 0 EOAF: End of acquisition flag
This bit is set by hardware when the acquisition of all enabled group is complete (all GxS bits
of all enabled analog I/O groups are set or when a max count error is detected). It is cleared
by software writing 1 to the bit EOAIC of the TSC_ICR register.
0: Acquisition is on-going or not started
1: Acquisition is complete
27.6.5

TSC I/O hysteresis control register (TSC_IOHCR)

Address offset: 0x10
Reset value: 0xFFFF FFFF
31 30 29
Res. Res. Res. Res.
15 14 13
G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1
rw rw rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:0 Gx_IOy: Gx_IOy Schmitt trigger hysteresis mode
Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is
694/742
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger
hysteresis.
0: Gx_IOy Schmitt trigger hysteresis disabled
1: Gx_IOy Schmitt trigger hysteresis enabled
(even if controlled by standard GPIO registers).
Doc ID 018940 Rev 1
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
Res. Res. Res. Res.
24 23 22 21
Res. G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1
rw rw rw
8 7 6 5
rw rw rw rw
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
Res. Res. Res. MCEF
rw
20 19 18 17
rw rw rw rw
4 3 2 1
rw rw rw rw
RM0091
16
Res.
0
EOAF
rw
16
rw
0
rw