RM0091
The asynchronous prescaler division factor is set to 128, and the synchronous division
factor to 256, to obtain an internal clock frequency of 1 Hz (ck_spre) with an LSE frequency
of 32.768 kHz.
The minimum division factor is 1 and the maximum division factor is 2
This corresponds to a maximum input frequency of around 4 MHz.
f
is given by the following formula:
ck_apre
The ck_apre clock is used to clock the binary RTC_SSR subseconds downcounter. When it
reaches 0, RTC_SSR is reloaded with the content of PREDIV_S.
f
is given by the following formula:
ck_spre
24.3.4
Real-time clock and calendar
The RTC calendar time and date registers are accessed through shadow registers which
are synchronized with PCLK (APB clock). They can also be accessed directly in order to
avoid waiting for the synchronization duration.
●
RTC_SSR for the subseconds
●
RTC_TR for the time
●
RTC_DR for the date
Every two RTCCLK periods, the current calendar value is copied into the shadow registers,
and the RSF bit of RTC_ISR register is set (see
in Stop and Standby mode. When exiting these modes, the shadow registers are updated
after up to 2 RTCCLK periods.
When the application reads the calendar registers, it accesses the content of the shadow
registers. It is possible to make a direct access to the calendar registers by setting the
BYPSHAD control bit in the RTC_CR register. By default, this bit is cleared, and the user
accesses the shadow registers.
When reading the RTC_SSR, RTC_TR or RTC_DR registers in BYPSHAD=0 mode, the
frequency of the APB clock (f
(f
RTCCLK
The shadow registers are reset by system reset.
24.3.5
Programmable alarm
The RTC unit provides programmable alarm: Alarm A.
The programmable alarm function is enabled through the ALRAE bit in the RTC_CR
register. The ALRAF is set to 1 if the calendar subseconds, seconds, minutes, hours, date or
day match the values programmed in the alarm registers RTC_ALRMASSR and
RTC_ALRMAR. Each calendar field can be independently selected through the MSKx bits
f
CK_SPRE
APB
).
Doc ID 018940 Rev 1
f
RTCCLK
f
=
-------------------------------------- -
CK_APRE
PREDIV_A
f
RTCCLK
=
----------------------------------------------------------------------------------------------
(
)
×
(
PREDIV_S
1
PREDIV_A
+
Section
) must be at least 7 times the frequency of the RTC clock
Real-time clock (RTC)
22
.
+
1
)
1
+
24.6.4). The copy is not performed
539/742
Need help?
Do you have a question about the STM32F05 series and is the answer not in the manual?
Questions and answers