Own Address 2 Register (I2Cx_Oar2) - STMicroelectronics STM32F05 series Reference Manual

RM0091
Bits 7:1 OA1[7:1]: Interface address
bits 7:1 of address
Note: These bits can be written only when OA1EN=0.
Bit 0 OA1[0]: Interface address
7-bit addressing mode: don't care
10-bit addressing mode: bit 0 of address
Note: This bit can be written only when OA1EN=0.
23.7.4

Own address 2 register (I2Cx_OAR2)

Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res.
15 14 13
OA2EN Res. Res.
rw
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 OA2EN: Own Address 2 enable
0: Own address 2 disabled. The received slave address OA2 is NACKed.
1: Own address 2 enabled. The received slave address OA2 is ACKed.
Bits 14:11 Reserved, must be kept at reset value.
Bits 10:8 OA2MSK[2:0]: Own Address 2 masks
000: No mask
001: OA2[1] is masked and don't care. Only OA2[7:2] are compared.
010: OA2[2:1] are masked and don't care. Only OA2[7:3] are compared.
011: OA2[3:1] are masked and don't care. Only OA2[7:4] are compared.
100: OA2[4:1] are masked and don't care. Only OA2[7:5] are compared.
101: OA2[5:1] are masked and don't care. Only OA2[7:6] are compared.
110: OA2[6:1] are masked and don't care. Only OA2[7] is compared.
111: OA2[7:1] are masked and don't care. No comparison is done, and all (except reserved)
7-bit received addresses are acknowledged.
Note: These bits can be written only when OA2EN=0.
Bits 7:1 OA2[7:1]: Interface address
bits 7:1 of address
Note: These bits can be written only when OA2EN=0.
Bit 0 Reserved, must be kept at reset value.
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
Res. Res. OA2MSK[2:0]
rw
As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and
0b1111xxx) are not acknowledged even if the comparison matches.
Doc ID 018940 Rev 1
Inter-integrated circuit (I
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
2
C) interface
20 19 18
Res. Res. Res. Res.
4 3 2
OA2[7:1]
rw
17 16
Res.
1 0
Res.
525/742