Figure 148. Capture/Compare Channel 1 Main Circuit; Figure 149. Output Stage Of Capture/Compare Channel (Channel 1) - STMicroelectronics STM32F05 series Reference Manual

General-purpose timer (TIM14)

Figure 148. Capture/compare channel 1 main circuit

read CCR1H
read CCR1L
CC1S[1]
CC1S[0]
IC1PS
CC1E
CC1G
TIM1_EGR

Figure 149. Output stage of capture/compare channel (channel 1)

CNT > CCR1
CNT = CCR1
The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
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S
read_in_progress
Capture/compare preload register
R
capture_transfer
input
mode
Capture/compare shadow register
OC1_REF
Output mode
controller
OC1M[2:0]
TIMx_CCMR1
Doc ID 018940 Rev 1
APB Bus
MCU-peripheral interface
8
8
compare_transfer
capture
Counter
To the master mode
controller
write CCR1H
S
write_in_progress
write CCR1L
R
CC1S[1]
output
mode
CC1S[0]
UEV
(from time
comparator
base unit)
CNT>CCR1
CNT=CCR1
0
Output
enable
circuit
1
CC1P
TIMx_CCER
CC1E TIMx_CCER
RM0091
OC1PE
OC1PE
TIM1_CCMR1
OC1
ai17720