Spi Interrupts; S Functional Description; S General Description; Table 91. Spi Interrupt Requests - STMicroelectronics STM32F05 series Reference Manual

Serial peripheral interface / inter-IC sound (SPI/I2S)
Note: When the SPI is in slave mode, the CRC calculator is sensitive to the SCK slave input clock
as soon as the CRCEN bit is set, and this is the case whatever the value of the SPE bit. In
order to avoid any wrong CRC calculation, the software must enable CRC calculation only
when the clock is stable (in steady state). When the SPI interface is configured as a slave,
the NSS internal signal needs to be kept low between the data phase and the CRC phase.
26.5

SPI interrupts

During SPI communication an interrupts can be generated by the following events:
●
Transmit TXFIFO ready to be loaded
●
Data received in Receive RXFIFO
●
Master mode fault
●
Overrun error
●
CRC error
●
TI frame format error
Interrupts can be enabled and disabled separately.
Table 91.
Transmit TXFIFO ready to be loaded
Data received in RXFIFO
Master Mode fault event
Overrun error
CRC error
TI frame format error
2
26.6 I

S functional description

2
26.6.1 I

S general description

The block diagram of the I
652/742
SPI interrupt requests
Interrupt event
2
S is shown in
Doc ID 018940 Rev 1
Event flag
TXE
RXNE
MODF
OVR
CRCERR
FRE
Figure 264.
RM0091
Enable Control bit
TXEIE
RXNEIE
ERRIE