Figure 239. Usart Example Of Synchronous Transmission; Figure 240. Usart Data Clock Timing Diagram (M=0) - STMicroelectronics STM32F05 series Reference Manual

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Figure 239. USART example of synchronous transmission

Figure 240. USART data clock timing diagram (M=0)

Clock (CPOL=0, CPHA=0)
Clock (CPOL=0, CPHA=1)
Clock (CPOL=1, CPHA=0)
Clock (CPOL=1, CPHA=1)
Universal synchronous asynchronous receiver transmitter (USART)
USART
Idle or preceding
Start
transmission
Data on TX
(from master)
Start
Data on RX
(from slave)
Capture Strobe
Doc ID 018940 Rev 1
RX
Data out
TX
Data in
Synchronous device
(e.g. slave SPI)
SCLK
Clock
M=0 (8 data bits)
0 1 2 3 4
LSB
0 1 2 3 4
LSB
Idle or next
Stop transmission
*
*
*
*
5 6 7
MSB Stop
5 6 7
MSB
*
* LBCL bit controls last data clock pulse
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