Pwm Mode; Figure 150. Output Compare Mode, Toggle On Oc1 - STMicroelectronics STM32F05 series Reference Manual

RM0091
The TIMx_CCRx register can be updated at any time by software to control the output
waveform, provided that the preload register is not enabled (OCxPE='0', else TIMx_CCRx
shadow register is updated only at the next update event UEV). An example is given in
Figure 150.

Figure 150. Output compare mode, toggle on OC1.

TIM1_CNT
TIM1_CCR1
oc1ref=OC1
17.3.8

PWM mode

Pulse Width Modulation mode allows you to generate a signal with a frequency determined
by the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx
output) by writing '110' (PWM mode 1) or '111' (PWM mode 2) in the OCxM bits in the
TIMx_CCMRx register. You must enable the corresponding preload register by setting the
OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in
upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event
occurs, before starting the counter, you have to initialize all the registers by setting the UG
bit in the TIMx_EGR register.
The OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register.
It can be programmed as active high or active low. The OCx output is enabled by the CCxE
bit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more
details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CNT ≤ TIMx_CCRx.
The timer is able to generate PWM in edge-aligned mode only since the counter is
upcounting.
Write B201h in the CC1R register
0039 003A
003B
003A
Doc ID 018940 Rev 1
General-purpose timer (TIM14)
Match detected on CCR1
Interrupt generated if enabled
B200 B201
B201
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