Figure 57. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr = 0X6; Figure 58. Counter Timing Diagram, Internal Clock Divided By 2; Figure 59. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36 - STMicroelectronics STM32F05 series Reference Manual

RM0091

Figure 57. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6

1.
Here, center-aligned mode 1 is used (for more details refer to

Figure 58. Counter timing diagram, internal clock divided by 2

Figure 59. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

1.
Center-aligned mode 2 or 3 is used with an UIF on overflow.
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter underflow
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Doc ID 018940 Rev 1
Advanced-control timers (TIM1)
04 03 02 01 00 01 02 03 04 05 06 05 04 03
Section 15.4: TIM1 registers on page
0003 0002 0001 0000 0001 0002 0003
0034 0035
265).
0036 0035
233/742