System And Memory Overview; System Architecture; Figure 1. System Architecture - STMicroelectronics STM32F05 series Reference Manual

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System and memory overview

2.1

System architecture

The main system consists of:
●
Two masters:
–
–
●
Four slaves:
–
–
–
–
These are interconnected using a multilayer AHB bus architecture as shown in
Figure 1.
Cortex
M0
DMA
Controller
(Channels
1 to 5)
System bus
This bus connects the system bus of the Cortex-M0 core (peripherals bus) to a BusMatrix
which manages the arbitration between the core and the DMA.
Cortex-M0 core AHB bus
GP-DMA (general-purpose DMA)
Internal SRAM
Internal Flash memory
AHB to APB, which connects all the APB peripherals
AHB dedicated to GPIO ports
System architecture
System bus
Busmatrix
DMA
Doc ID 018940 Rev 1
AHB2 bus
AHB2APB
APB bus
Bridge
Reset and
clock
controller
(RCC)
Touch
sensing
controller
(TSC)
CRC
DMA request
System and memory overview
FLITF
Flash memory
Flash interface
SRAM
GPIO Ports
A,B,C,D,F
SYSCFG
ADC
DAC
COMP
TIM1
TIM2,TIM3
TIM14,TIM15,TIM16,TIM17
TIM6
IWWDG
WWDG
RTC
I2C1, I2C2
USART1, USART2
SPI1/I2S1, SPI2
HDMI-CEC
DBGMCU
Figure 1:
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