Clock Sources; Figure 162. Update Rate Examples Depending On Mode And Timx_Rcr Register Settings - STMicroelectronics STM32F05 series Reference Manual

General-purpose timers (TIM15/16/17)
Figure 162. Update rate examples depending on mode and TIMx_RCR register
18.4.4

Clock sources

The counter clock can be provided by the following clock sources:
●
Internal clock (CK_INT)
●
External clock mode1: external input pin
●
Internal trigger inputs (ITRx) (only for TIM15): using one timer as the prescaler for
another timer, for example, you can configure TIM1 to act as a prescaler for TIM15.
Refer to
Internal clock source (CK_INT)
If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1
register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed
only by software (except UG which remains cleared automatically). As soon as the CEN bit
is written to 1, the prescaler is clocked by the internal clock CK_INT.
Figure 17.3.4
without prescaler.
384/742
settings
Counter
TIMx_CNT
UEV
TIMx_RCR = 0
TIMx_RCR = 1
UEV
UEV
TIMx_RCR = 2
UEV
TIMx_RCR = 3
TIMx_RCR
= 3
and
re-synchronization
UEV
UEV
Update Event: Preload registers transferred to active registers and update interrupt generated
Using one timer as prescaler for another
shows the behavior of the control circuit and the upcounter in normal mode,
Doc ID 018940 Rev 1
Edge-aligned mode
Upcounting
(by SW)
for more details.
RM0091
ai17332