STMicroelectronics STM32F05 series Reference Manual page 553

RM0091
Bit 16 ADD1H: Add 1 hour (summer time change)
Bit 15 TSIE: Time-stamp interrupt enable
Bit 14 Reserved, must be kept at reset value
Bit 13 Reserved, must be kept at reset value
Bit 12 ALRAIE: Alarm A interrupt enable
Bit 11 TSE: timestamp enable
Bit 10 Reserved, must be kept at reset value
Bit 9 Reserved, must be kept at reset value
Bit 8 ALRAE: Alarm A enable
Bit 7 Reserved, must be kept at reset value.
Bit 6 FMT: Hour format
Bit 5 BYPSHAD: Bypass the shadow registers
Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK,
Bit 4 REFCKON: RTC_REFIN reference clock detection enable (50 or 60 Hz)
Note: PREDIV_S must be 0x00FF.
Bit 3 TSEDGE: Time-stamp event active edge
Bits 2:0 Reserved, must be kept at reset value
When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit
is always read as 0.
0: No effect
1: Adds 1 hour to the current time. This can be used for summer time change
0: Time-stamp Interrupt disable
1: Time-stamp Interrupt enable
0: Alarm A interrupt disabled
1: Alarm A interrupt enabled
0: timestamp disable
1: timestamp enable
0: Alarm A disabled
1: Alarm A enabled
0: 24 hour/day format
1: AM/PM hour format
0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from
the shadow registers, which are updated once every two RTCCLK cycles.
1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken
directly from the calendar counters.
BYPSHAD must be set to '1'.
0: RTC_REFIN detection disabled
1: RTC_REFIN detection enabled
0: RTC_TS input rising edge generates a time-stamp event
1: RTC_TS input falling edge generates a time-stamp event
TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting.
Doc ID 018940 Rev 1
Real-time clock (RTC)
553/742