STMicroelectronics STM32F05 series Reference Manual page 523

RM0091
Bit 15 NACK: NACK generation (slave mode)
Note: Writing '0' to this bit has no effect.
Bit 14 STOP: Stop generation (master mode)
Note: Writing '0' to this bit has no effect.
Bit 13 START: Start generation
– If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a
– Otherwise setting this bit will generate a START condition once the bus is free.
Note: Writing '0' to this bit has no effect.
Bit 12 HEAD10R: 10-bit address header only read direction (master receiver mode)
Note: Changing this bit when the START bit is set is not allowed.
Bit 11 ADD10: 10-bit addressing mode (master mode)
Note: Changing this bit when the START bit is set is not allowed.
Bit 10 RD_WRN: Transfer direction (master mode)
Note: Changing this bit when the START bit is set is not allowed.
The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP
condition or an Address Matched is received, or when PE=0 or SWRST is set.
0: an ACK is sent after current received byte.
1: a NACK is sent after current received byte.
This bit is used in slave mode only: in master receiver mode, NACK is automatically
generated after last byte preceding STOP or RESTART condition, whatever the NACK
bit value.
When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically
generated whatever the NACK bit value.
When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value
does not depend on the NACK value.
The bit is set by software, cleared by hardware when a Stop condition is detected, or when
PE = 0 or SWRST is set.
In Master Mode:
0: No Stop generation.
1: Stop generation after current byte transfer.
This bit is set by software, and cleared by hardware after the Start followed by the address
sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0 or
SWRST is set. It can also be cleared by software by writing '1' to the ADDRCF bit in the
I2Cx_ICR register.
0: No Start generation.
1: Restart/Start generation:
Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer.
The START bit can be set even if the bus is BUSY or I2C is in slave mode.
This bit has no effect when RELOAD is set.
0: The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit
address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction.
1: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction.
0: The master operates in 7-bit addressing mode,
1: The master operates in 10-bit addressing mode
0: Master requests a write transfer.
1: Master requests a read transfer.
Doc ID 018940 Rev 1
Inter-integrated circuit (I
2
C) interface
523/742