Figure 228. Usart Block Diagram - STMicroelectronics STM32F05 series Reference Manual

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Figure 228. USART block diagram

IrDA
SIR
TX
ENDEC
RX
block
nRTS
Hardware
/DE
flow
nCTS
controller
USARTDIV = DIV_Mantissa + (DIV_Fraction / 8 × (2 – OVER8))
Universal synchronous asynchronous receiver transmitter (USART)
PWDATA
Write
(CPU or DMA)
Transmit data register (TDR)
Transmit Shift Register
USART_CR3 register
USART_CR2 register
Transmit
control
USART_CR1 register
USART
interrupt
control
Transmitter
clock
/
[8 x (2 - OVER8)]
SAMPLING
DIVIDER
f
PCLKx(x=1,2)
Doc ID 018940 Rev 1
Read
(CPU or DMA)
Receive data register (RDR)
Receive Shift Register
USART_GTPR register
GT PSC
USART_CR1 register
Wakeup
unit
USART_BRR register
TE
/
USARTDIV
15
RE
Conventional baud rate generator
PRDATA
(Data register) DR
SCLK control
USART_CR2 register
Receiver
Receiver clock
control
USART_ISR register
Tra nsmitter rate
control
BRR[15:0]
Receiver rate
control
SCLK
MS19821V1
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