STMicroelectronics STM32F05 series Reference Manual page 91

RM0091 Reset and clock control (RCC)
HDMI CEC, USART1 and I2C1 have the capability to enable the HSI oscillator even when
the MCU is in Stop mode (if HSI is selected as the clock source for that peripheral).
HDMI CEC and USART1 can also be driven by the LSE oscillator when the system is in
Stop mode (if LSE is selected as clock source for that peripheral) and the LSE oscillator is
enabled (LSEON) but they do not have the capability to turn on the LSE oscillator.
Standby mode stops all the clocks in the core supply domain and disables the PLL and the
HSI, HSI14 and HSE oscillators.
The CPU's deepsleep mode can be overridden for debugging by setting the DBG_STOP or
DBG_STANDBY bits in the DBGMCU_CR register.
When waking up from deepsleep after an interrupt (Stop mode) or reset (Standby mode),
the HSI oscillator is selected as system clock.
If a Flash programming operation is on going, deepsleep mode entry is delayed until the
Flash interface access is finished. If an access to the APB domain is ongoing, deepsleep
mode entry is delayed until the APB access is finished.
Doc ID 018940 Rev 1 91/742