Rtc Sub Second Register (Rtc_Ssr) - STMicroelectronics STM32F05 series Reference Manual

Real-time clock (RTC)
24.6.8

RTC sub second register (RTC_SSR)

Address offset: 0x28
Power-on reset value: 0x0000 0000
System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.
31 30 29
Res. Res. Res. Res.
15 14 13
r r r
Bits31:16 Reserved, must be kept at reset value
Bits 15:0 SS: Sub second value
SS[15:0] is the value in the synchronous prescaler's counter. The fraction of a second is
given by the formula below:
Second fraction = ( PREDIV_S - SS ) / ( PREDIV_S + 1 )
Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct
560/742
28 27 26 25
Res. Res. Res.
12 11 10 9
r r r r
time/date is one second less than as indicated by RTC_TR/RTC_DR.
Doc ID 018940 Rev 1
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
SS[15:0]
r r r r
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
r r r r
RM0091
16
Res.
0
r