Rising Trigger Selection Register (Exti_Rtsr); Falling Trigger Selection Register (Exti_Ftsr) - STMicroelectronics STM32F05 series Reference Manual

Interrupts and events
11.3.3

Rising trigger selection register (EXTI_RTSR)

Address offset: 0x08
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
TR15 TR14 TR13 TR12
rw rw rw
Bits 31:20 Reserved, must be kept at reset value.
Bits 17:0 TRx: Rising trigger event configuration bit of line x (x = 17 to 0)
Note: The external wakeup lines are edge triggered. No glitches must be generated on these
lines. If a rising edge on an external interrupt line occurs during a write operation to the
EXTI_RTSR register, the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this case, both
generate a trigger condition.
11.3.4

Falling trigger selection register (EXTI_FTSR)

Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
TR15 TR14 TR13 TR12
rw rw rw
Bits 31:20 Reserved, must be kept at reset value.
Bits 17:0 TRx: Falling trigger event configuration bit of line x (x = 17 to 0)
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28 27 26 25
Res. Res. Res.
12 11 10 9
TR11 TR10 TR9
rw rw rw rw
Bit 19 TR19: Rising trigger event configuration bit of line 19
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line.
Bits 18 Reserved, must be kept at reset value.
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line.
28 27 26 25
Res. Res. Res.
12 11 10 9
TR11 TR10 TR9
rw rw rw rw
Bit 19 TR19: Falling trigger event configuration bit of line 19
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line.
Bits 18 Reserved, must be kept at reset value.
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line.
Doc ID 018940 Rev 1
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
TR8 TR7 TR6 TR5
rw rw rw rw
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
TR8 TR7 TR6 TR5
rw rw rw rw
20 19 18 17
Res. TR19 Res. TR17
rw rw
4 3 2 1
TR4 TR3 TR2 TR1
rw rw rw rw
20 19 18 17
Res. TR19 Res. TR17
rw rw
4 3 2 1
TR4 TR3 TR2 TR1
rw rw rw rw
RM0091
16
TR16
rw
0
TR0
rw
16
TR16
rw
0
TR0
rw