Table 66. I2C-Smbus Specification Clock Timings; Figure 209. Master Clock Generation - STMicroelectronics STM32F05 series Reference Manual

Inter-integrated circuit (I

Figure 209. Master clock generation

SCL high level detected
SCL
SCL released
SCL high level detected
SCLH counter starts
Caution: In order to be I2C or SMBus compliant, the master clock must respect the timings given
below:
Table 66. I2C-SMBUS specification clock timings
Symbol
f SCL clock frequency
SCL
Hold time (repeated) START
t
HD:STA
condition
Set-up time for a repeated START
t
SU:STA
condition
t
Set-up time for STOP condition
SU:STO
488/742
2
C) interface
SCL master clock generation
SCLH counter starts
t
SYNC2 SCLH
t
SYNC1
SCL low level detected
SCLL counter starts
SCL driven low
SCL master clock synchronization
SCLH
SCLL
SCL driven low by
another device
SCL low level detected
SCLL counter starts
Parameter
Doc ID 018940 Rev 1
SCLL
SCL high level detected
SCLH counter starts
SCLH
SCL low level detected
SCLL counter starts
SCL released
Standard Fast Mode
Min Max Min Max
100 400
4.0 0.6
4.7 0.6
4.0 0.6
SCL high level detected
SCLH counter starts
SCLH
SCLL
SCL driven low by
another device
Fast Mode
SMBUS
Plus
Min Max Min Max
1000
0.26 4.0
0.26 4.7
0.26 4.0
RM0091
MS19858V1
Unit
100 kHz
µs
µs
µs