STMicroelectronics STM32F05 series Reference Manual page 98

Reset and clock control (RCC)
Bits 15:14
Bit 13 HSI14RDYIE: HSI14 ready interrupt enable
Bit 12 PLLRDYIE: PLL ready interrupt enable
Bit 11 HSERDYIE: HSE ready interrupt enable
Bit 10 HSIRDYIE: HSI ready interrupt enable
Bit 9 LSERDYIE: LSE ready interrupt enable
Bit 8 LSIRDYIE: LSI ready interrupt enable
Bit 7 CSSF: Clock security system interrupt flag
Bit 6
Bit 5
98/742
Reserved, must be kept at reset value.
Set and cleared by software to enable/disable interrupt caused by the HSI14 oscillator
stabilization.
0: HSI14 ready interrupt disabled
1: HSI14 ready interrupt enabled
Set and cleared by software to enable/disable interrupt caused by PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
Set and cleared by software to enable/disable interrupt caused by the HSE oscillator
stabilization.
0: HSE ready interrupt disabled
1: HSE ready interrupt enabled
Set and cleared by software to enable/disable interrupt caused by the HSI oscillator
stabilization.
0: HSI ready interrupt disabled
1: HSI ready interrupt enabled
Set and cleared by software to enable/disable interrupt caused by the LSE oscillator
stabilization.
0: LSE ready interrupt disabled
1: LSE ready interrupt enabled
Set and cleared by software to enable/disable interrupt caused by the LSI oscillator
stabilization.
0: LSI ready interrupt disabled
1: LSI ready interrupt enabled
Set by hardware when a failure is detected in the HSE oscillator.
Cleared by software setting the CSSC bit.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure
Reserved, must be kept at reset value.
HSI14RDYF: HSI14 ready interrupt flag
Set by hardware when the HSI14 becomes stable and HSI14RDYDIE is set in a response
to setting the HSI14ON bit (refer to
HSI14ON is not set but the HSI14 oscillator is enabled by the peripheral through a clock
request, this bit is not set and no interrupt is generated.
Cleared by software setting the HSI14RDYC bit.
0: No clock ready interrupt caused by the HSI14 oscillator
1: Clock ready interrupt caused by the HSI14 oscillator
Doc ID 018940 Rev 1
Clock configuration register 2
RM0091
(RCC_CFGR2). When