STMicroelectronics STM32F05 series Reference Manual page 93

RM0091
Bit 17 HSERDY: HSE clock ready flag
Set by hardware to indicate that the HSE oscillator is stable. This bit needs 6 cycles of the
HSE oscillator clock to fall down after HSEON reset.
0: HSE oscillator not ready
1: HSE oscillator ready
Bit 16 HSEON: HSE clock enable
Set and cleared by software.
Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This
bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.
0: HSE oscillator OFF
1: HSE oscillator ON
Bits 15:8 HSICAL[7:0]: HSI clock calibration
These bits are initialized automatically at startup.
Bits 7:3 HSITRIM[4:0]: HSI clock trimming
These bits provide an additional user-programmable trimming value that is added to the
HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature
that influence the frequency of the HSI.
The default value is 16, which, when added to the HSICAL value, should trim the HSI to 8
MHz ± 1%. The trimming step (F
steps.
Bit 2 Reserved, must be kept at reset value.
Bit 1 HSIRDY: HSI clock ready flag
Set by hardware to indicate that HSI oscillator is stable. After the HSION bit is cleared,
HSIRDY goes low after 6 HSI oscillator clock cycles.
0: HSI oscillator not ready
1: HSI oscillator ready
Bit 0 HSION: HSI clock enable
Set and cleared by software.
Set by hardware to force the HSI oscillator ON when leaving Stop or Standby mode or in
case of failure of the HSE crystal oscillator used directly or indirectly as system clock. This
bit cannot be reset if the HSI is used directly or indirectly as system clock or is selected to
become the system clock.
0: HSI oscillator OFF
1: HSI oscillator ON
) is around 40 kHz between two consecutive HSICAL
hsitrim
Doc ID 018940 Rev 1
Reset and clock control (RCC)
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