Figure 47. Counter Timing Diagram, Internal Clock Divided By 2; Figure 48. Counter Timing Diagram, Internal Clock Divided By 4; Figure 49. Counter Timing Diagram, Internal Clock Divided By N - STMicroelectronics STM32F05 series Reference Manual

Advanced-control timers (TIM1)

Figure 47. Counter timing diagram, internal clock divided by 2

Figure 48. Counter timing diagram, internal clock divided by 4

Figure 49. Counter timing diagram, internal clock divided by N

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CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
CK_PSC
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
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