Figure 207. Transfer Sequence Flowchart For Slave Receiver With Nostretch=1; Figure 208. Transfer Bus Diagrams For I2C Slave Receiver - STMicroelectronics STM32F05 series Reference Manual

Inter-integrated circuit (I

Figure 207. Transfer sequence flowchart for slave receiver with NOSTRETCH=1

Figure 208. Transfer bus diagrams for I2C slave receiver

RXNE
EV1: ADDR ISR: check ADDCODE and DIR, set ADDRCF
EV2: RXNE ISR: rd data1
EV3 : RXNE ISR: rd data2
EV4: RXNE ISR: rd data3
Example I2C slave receiver 3 bytes, NOSTRETCH=1:
RXNE
EV1: RXNE ISR: rd data1
EV2: RXNE ISR: rd data2
EV3: RXNE ISR: rd data3
EV4: STOPF ISR: set STOPCF
486/742
2
C) interface
I2Cx_ISR.RXNE
=1?
Yes
Read I2Cx_RXDR.RXDATA
ADDR
data1
S Address A
EV1
RXNE
data1
Address A
S
Doc ID 018940 Rev 1
Slave reception
Slave initialization
No
RXNE
RXNE
data2
A A
EV2
RXNE RXNE
data2 data3
A A
EV1 EV2
No
I2Cx_ISR.STOPF
=1?
Yes
Set I2Cx_ICR.STOPCF
RXNE
data3
A
EV3 EV4
A P
EV3
RM0091
MS19856V1
transmission
reception
SCL stretch
legend:
transmission
reception
SCL stretch
MS19857V1