Figure 206. Transfer Sequence Flowchart For Slave Receiver With Nostretch=0 - STMicroelectronics STM32F05 series Reference Manual

Advanced arm-based 32-bit mcus
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RM0091
Slave receiver
RXNE is set in I2Cx_ISR when the I2Cx_RXDR is full, and generates an interrupt if RXIE is
set in I2Cx_CR1. RXNE is cleared when I2Cx_RXDR is read.
When a STOP is received and STOPIE is set in I2Cx_CR1, STOPF is set in I2Cx_ISR and
an interrupt is generated.

Figure 206. Transfer sequence flowchart for slave receiver with NOSTRETCH=0

Slave reception
Slave initialization
No
I2Cx_ISR.ADDR
=1?
Yes
Read ADDCODE and DIR in I2Cx_ISR
Set I2Cx_ICR.ADDRCF
I2Cx_ISR.RXNE
=1?
Yes
Write I2Cx_RXDR.RXDATA
Doc ID 018940 Rev 1
Inter-integrated circuit (I
No
2
C) interface
SCL
stretched
MS19855V1
485/742

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