STMicroelectronics STM32F05 series Reference Manual page 651

RM0091
CRC transfer managed by CPU
Communication starts and continues normally until the last data frame has to been sent or
received in the SPIx_DR register. Then CRCNEXT bit has to be set in the SPIx_CR1
register to indicate that the CRC frame transaction follows after the transaction of the
currently processed data frame. Setting the CRCNEXT bit must be done before the end of
the last data frame transaction. CRC calculation is frozen during CRC transaction.
The received CRC is stored in the RXFIFO like a data byte or word. That is why in CRC
mode only, the reception buffer has to be considered as a single 16-bit buffer used to receive
only one data frame at a time.
A CRC-format transaction usually takes one more data frame to communicate at the end of
data sequence. However, when setting an 8-bit data frame checked by 16-bit CRC, two
more frames are necessary to send the complete CRC.
When the last CRC data is received, an automatic check is performed comparing the
received value and the value in the SPIx_RXCRC register. Software has to check the
CRCERR flag in the SPIx_SR register to determine if the data transfers were corrupted or
not. Software clears the CRCERR flag by writing '0' to it.
After the CRC reception, the CRC value is stored in the RXFIFO and must be read in the
SPIx_DR register in order to clear the RXNE flag.
CRC transfer managed by DMA
When SPI communication is enabled with CRC communication and DMA mode, the
transmission and reception of the CRC at the end of communication are automatic. The
CRCNEXT bit does not have to be handled by the software. The counter for the SPI
transmission DMA channel has to be set to the number of data frames to transmit excluding
the CRC frame. The counter of the reception DMA channel needs to be loaded with the
number of data frames to receive including the CRC one(s), which means, for example, in
the specific case of 8-bit data frame checked by 16-bit CRC:
DMA_RX = Numb_of_data + 2
On the receiver side, the received CRC value is stored in the memory after the transaction.
At the end of data and CRC transfers, the CRCERR flag in the SPIx_SR register is set if
corruption occurs during the transfer.
Resetting the SPIx_TXCRC and SPIx_RXCRC values
The SPIx_TXCRC and SPIx_RXCRC values are cleared automatically when new data is
sampled after a CRC phase. This allows the use of DMA circular mode (not available in
receive-only mode) in order to transfer data without any interruption, (several data blocks
covered by intermediate CRC checking phases).
If the SPI is disabled during a communication the following sequence must be followed:
–
–
–
–
Disable the SPI
Clear the CRCEN bit
Enable the CRCEN bit
Enable the SPI
Doc ID 018940 Rev 1
Serial peripheral interface / inter-IC sound (SPI/I2S)
651/742