Wakeup Event Management; Asynchronous Internal Interrupts; Figure 20. Exti External Interrupt/Event Block Diagram - STMicroelectronics STM32F05 series Reference Manual

Interrupts and events

Figure 20. EXTI external interrupt/event block diagram

PCLK
To NVIC interrupt
controller
23
23
11.2.3

Wakeup event management

The STM32F05xxx is able to handle external or internal events in order to wake up the core
(WFE). The wakeup event can be generated either by:
●
enabling an interrupt in the peripheral control register but not in the NVIC, and enabling
the SEVONPEND bit in the Cortex-M0 System Control register. When the MCU
resumes from WFE, the EXTI peripheral interrupt pending bit and the peripheral NVIC
IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be
cleared.
●
or by configuring an external or internal EXTI line in event mode. When the CPU
resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or
the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is
not set.
11.2.4

Asynchronous Internal Interrupts

Some communication peripherals (UART, I2C, CEC) are able to generate events when the
system is in run mode and also when the system is in stop mode allowing to wake up the
system from stop mode.
To accomplish this, the peripheral is asked to generate both a synchronized (to the system
clock, e.g. APB clock) and an asynchronous version of the event.
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23
Pending Interrupt
request
register register
23
Pulse
generator 23
Event
mask
register
Doc ID 018940 Rev 1
AMBA APB bus
Peripheral interface
23
23
Software
interrupt
mask
event selection
Register
23
23
23 23
Rising Falling
trigger trigger
selection
regsiter regsiter
23 23
Edge detect
circuit
RM0091
Input
line
MS19952V1