Figure 109. Counter Timing Diagram, Update Event With Arpe=1 (Counter Underflow); Figure 110. Counter Timing Diagram, Update Event With Arpe=1 (Counter Overflow) - STMicroelectronics STM32F05 series Reference Manual

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Figure 109. Counter timing diagram, Update event with ARPE=1 (counter underflow)

Figure 110. Counter timing diagram, Update event with ARPE=1 (counter overflow)

CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
Write a new value in TIMx_ARR
Auto-reload active register
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
Write a new value in TIMx_ARR
Auto-reload active register
Doc ID 018940 Rev 1
General-purpose timers (TIM2 and TIM3)
06 05 04 03 02 01 00 01 02 03 04 05 06 07
FD
FD
F7 F8 F9 FA FB FC 36 35 34 33 32 31 30 2F
FD
FD
36
36
36
36
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