Debug Support For Low-Power Modes; Debug Support For Timers, Watchdog And I 2 C - STMicroelectronics STM32F05 series Reference Manual

RM0091
29.9.1

Debug support for low-power modes

To enter low-power mode, the instruction WFI or WFE must be executed.
The MCU implements several low-power modes which can either deactivate the CPU clock
or reduce the power of the CPU.
The core does not allow FCLK or HCLK to be turned off during a debug session. As these
are required for the debugger connection, during a debug, they must remain active. The
MCU integrates special means to allow the user to debug software in low-power modes.
For this, the debugger host must first set some debug configuration registers to change the
low-power mode behavior:
●
In Sleep mode : FCLK and HCLK are still active. Consequently, this mode does not
impose any restrictions on the standard debug features.
●
In Stop/Standby mode, the DBG_STOP bit must be previously set by the debugger.
This enables the internal RC oscillator clock to feed FCLK and HCLK in Stop mode.
29.9.2 Debug support for timers, watchdog and I
During a breakpoint, it is necessary to choose how the counter of timers and watchdog
should behave:
●
They can continue to count inside a breakpoint. This is usually required when a PWM is
controlling a motor, for example.
●
They can stop to count inside a breakpoint. This is required for watchdog purposes.
2
For the I C, the user can choose to block the SMBUS timeout during a breakpoint.
Doc ID 018940 Rev 1
Debug support (DBG)
2
C
727/742