I 2 S Status Flags - STMicroelectronics STM32F05 series Reference Manual

RM0091
For more details about the read operations depending the I
to Section 26.6.2: Supported audio
If data are received while the preceding received data have not yet been read, an overrun is
generated and the OVR flag is set. If the bit ERRIE is set in the SPIx_CR2 register, an
interrupt is generated to indicate the error.
To switch off the I
the last RXNE = 1.
Note: The external master components should have the capability of sending/receiving data in 16-
bit or 32-bit packets via an audio channel.
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26.6.6 I S status flags
Three status flags are provided for the application to fully monitor the state of the I
Busy flag (BSY)
The BSY flag is set and cleared by hardware (writing to this flag has no effect). It indicates
the state of the communication layer of the I
When BSY is set, it indicates that the I
master receive mode (I2SCFG = 11) where the BSY flag is kept low during reception.
The BSY flag is useful to detect the end of a transfer if the software needs to disable the I
This avoids corrupting the last transfer. For this, the procedure described below must be
strictly respected.
The BSY flag is set when a transfer starts, except when the I
The BSY flag is cleared:
●
When a transfer completes (except in master transmit mode, in which the
communication is supposed to be continuous)
●
When the I
When communication is continuous:
●
In master transmit mode, the BSY flag is kept high during all the transfers
● In slave mode, the BSY flag goes low for one I
Note: Do not use the BSY flag to handle each data transmission or reception. It is better to use the
TXE and RXNE flags instead.
Tx buffer empty flag (TXE)
When set, this flag indicates that the Tx buffer is empty and the next data to be transmitted
can then be loaded into it. The TXE flag is reset when the Tx buffer already contains data to
be transmitted. It is also reset when the I
RX buffer not empty (RXNE)
When set, this flag indicates that there are valid received data in the RX Buffer. It is reset
when SPIx_DR register is read.
Serial peripheral interface / inter-IC sound (SPI/I2S)
protocols.
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S in reception mode, I2SE has to be cleared immediately after receiving
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S is disabled
Doc ID 018940 Rev 1
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S standard mode selected, refer
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S.
2
S is busy communicating. There is one exception in
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S clock cycle between each transfer
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S is disabled (I2SE bit is reset).
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S is in master receiver mode.
S bus.
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S.
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