I 2 C Debug Mode; I 2 C Registers; Control Register 1 (I2Cx_Cr1) - STMicroelectronics STM32F05 series Reference Manual

RM0091
2
23.6 I C debug mode
When the microcontroller enters debug mode (core halted), the SMBus timeout either
continues to work normally or stops, depending on the DBG_I2Cx_SMBUS_TIMEOUT
configuration bits in the DBG module..
2
23.7 I C registers
Refer to
The peripheral registers are accessed by words (32-bit).
23.7.1

Control register 1 (I2Cx_CR1)

Address offset: 0x00
Reset value: 0x0000 0000
31 30 29
Res. Res. Res.
15 14 13
RXDMA TXDMA
SWRST
EN EN
rw rw w
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 PECEN: PEC enable
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
Bit 22 ALERTEN: SMBus alert enable
Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO.
Bit 21 SMBDEN: SMBus Device Default address enable
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
Section 1.1 on page 34
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
ANF
DNF
OFF
rw rw
0: PEC calculation disabled
1: PEC calculation enabled
Please refer to Section 23.3: I2C
Device mode (SMBHEN=0):
0: Releases SMBA pin high and Alert Response Address Header disabled: 0001100x
followed by NACK.
1: Drives SMBA pin low and Alert Response Address Header enables: 0001100x followed
by ACK.
Host mode (SMBHEN=1):
0: SMBus Alert pin (SMBA) not supported.
1: SMBus Alert pin (SMBA) supported.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
Please refer to Section 23.3: I2C
0: Device default address disabled. Address 0b1100001x is NACKed.
1: Device default address enabled. Address 0b1100001x is ACKed.
Please refer to Section 23.3: I2C
Doc ID 018940 Rev 1
Inter-integrated circuit (I
for a list of abbreviations used in register descriptions.
24 23 22
ALERT SMBD
Res. PECEN
EN
rw rw
8 7 6
STOP
ERRIE TCIE
rw rw
implementation.
implementation.
implementation.
21 20 19 18
WUP
SMBH
GCEN
EN EN
EN
rw rw rw rw
5 4 3 2
NACK ADDR
RXIE
IE IE IE
rw rw rw rw
2
C) interface
17 16
NOSTR
SBC
ETCH
rw rw
1 0
TXIE PE
rw rw
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