Timing Register (I2Cx_Timingr) - STMicroelectronics STM32F05 series Reference Manual

Inter-integrated circuit (I
23.7.5

Timing register (I2Cx_TIMINGR)

Address offset: 0x10
Reset value: 0x0000 0000
31 30 29 28
PRESC[3:0]
rw
15 14 13 12
SCLH[7:0]
Bits 31:28 PRESC[3:0]: Timing prescaler
This field is used to prescale I2CCLK in order to generate the clock period t
data setup and hold counters (refer to
level counters (refer to
t
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:20 SCLDEL[3:0]: Data setup time
This field is used to generate a delay t
transmission mode.
t
Note: t
Bits 19:16 SDADEL[3:0]: Data hold time
This field is used to generate the delay t
transmission mode.
t
Note: SDADEL is used to generate t
Bits 15:8 SCLH[7:0]: SCL high period (master mode)
This field is used to generate the SCL high period in master mode.
t
Note: SCLH is also used to generate t
Bits 7:0 SCLL[7:0]: SCL low period (master mode)
This field is used to generate the SCL low period in master mode.
t
Note: SCLL is also used to generate t
Note: This register must be configured when the I2C is disabled (PE = 0).
526/742
2
C) interface
27 26 25
Res. Res. Res.
11 10 9
rw
I2C master initialization on page
= (PRESC+1) x t
PRESC I2CCLK
= (SCLDEL+1) x t
SCLDEL
is used to generate t
SCLDEL
= SDADEL x t
SDADEL PRESC
= (SCLH+1) x t
SCLH PRESC
= (SCLL+1) x t
SCLL PRESC
Doc ID 018940 Rev 1
24 23 22
Res. SCLDEL[3:0]
rw
8 7 6
I2C timings on page
between SDA edge and SCL rising edge in
SCLDEL
PRESC
timing.
SU:DAT
between SCL falling edge SDA edge in
SDADEL
timing.
HD:DAT
and t
SU:STO HD:STA
and t
BUF SU:STA
21 20 19 18
SDADEL[3:0]
5 4 3 2
SCLL[7:0]
rw
473) and for SCL high and low
487).
timing.
timings.
RM0091
17 16
rw
1 0
used for
PRESC