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Independent watchdog (IWDG)
21.4.4
Status register (IWDG_SR)
Address offset: 0x0C
Reset value: 0x0000 0000 (not reset by Standby mode)
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:3 Reserved, must be kept at reset value.
Bit 2 WVU: Watchdog counter window value update
This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset
by hardware when the reload value update operation is completed in the V
(takes up to 5 RC 40 kHz cycles).
Window value can be updated only when WVU bit is reset.
this bit is generated only if generic "window" = 1
Bit 1 RVU: Watchdog counter reload value update
This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset
by hardware when the reload value update operation is completed in the V
(takes up to 5 RC 40 kHz cycles).
Reload value can be updated only when RVU bit is reset.
Bit 0 PVU: Watchdog prescaler value update
This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is
reset by hardware when the prescaler update operation is completed in the V
domain (takes up to 5 RC 40 kHz cycles).
Prescaler value can be updated only when PVU bit is reset.
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28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Doc ID 018940 Rev 1
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
Res.
Res.
Res.
Res.
20
19
18
17
Res.
Res.
Res.
Res.
4
3
2
1
Res.
Res.
WVU
RVU
r
r
voltage domain
DD
voltage domain
DD
voltage
DD
RM0091
16
Res.
0
PVU
r
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