Option Byte Register (Flash_Obr) - STMicroelectronics STM32F05 series Reference Manual

RM0091
3.5.7

Option byte register (FLASH_OBR)

Address offset 0x1C
Reset value: 0x03FF FFF2
The reset value of this register depends on the value programmed in the option byte and the
OPTERR bit reset value depends on the comparison of the option byte and its complement
during the option byte loading phase.
31 30 29
r r r
15 14 13
r
Bits 31:24 Data1
Bits 23:16 Data0
Bits 15:8 User option bytes :
28 27 26 25
Data1
r r r r
12 11 10 9
r r r
Bit 15 : reserved
Bit 14 : RAM_PARITY_CHECK
Bit 13 : VDDA_MONITOR
Bit 12 : nBOOT1
Bit 11 : reserved
Bit 10 : nRST_STDBY
Bit 9 : nRST_STOP
Bit 8 : WDG_SW
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:1 RDPRT[2:1]: Read protection level status
00: Read protection level 0 is enabled (ST production configuration)
01: Read protection level 1 is enabled
11: Read protection level 2 is enabled.
Bit 0 OPTERR: Option byte error
When set, this indicates that the loaded option byte and its complement do not
match. The corresponding byte and its complement are read as 0xFF in the
FLASH_OBR or FLASH_WRPR register.
Doc ID 018940 Rev 1
24 23 22 21
r r r r
8 7 6 5
r
Embedded Flash memory
20 19 18 17
Data0
r r r r
4 3 2 1
r r
16
r
0
r
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