Rcc Registers; Clock Control Register (Rcc_Cr) - STMicroelectronics STM32F05 series Reference Manual

Reset and clock control (RCC)
7.4

RCC registers

Refer to
7.4.1

Clock control register (RCC_CR)

Address offset: 0x00
Reset value: 0x0000 XX83 where X is undefined.
Access: no wait state, word, half-?word and byte access
31 30 29
Res Res Res Res
15 14 13
r r r
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 PLLRDY: PLL clock ready flag
Set by hardware to indicate that the PLL is locked.
0: PLL unlocked
1: PLL locked
Bit 24 PLLON: PLL enable
Set and cleared by software to enable PLL.
Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the
PLL clock is used as system clock or is selected to become the system clock.
0: PLL OFF
1: PLL ON
Bits 23:20 Reserved, must be kept at reset value.
Bit 19 CSSON: Clock security system enable
Set and cleared by software to enable the clock security system. When CSSON is set, the
clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by
hardware if a HSE clock failure is detected.
0: Clock detector OFF
1: Clock detector ON (Clock detector ON if the HSE oscillator is ready , OFF if not).
Bit 18 HSEBYP: HSE crystal oscillator bypass
Set and cleared by software to bypass the oscillator with an external clock. The external
clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit
can be written only if the HSE oscillator is disabled.
0: HSE crystal oscillator not bypassed
1: HSE crystal oscillator bypassed with external clock
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Section 1.1 on page 34
28 27 26 25
PLL
Res Res
RDY
r
12 11 10 9
HSICAL[7:0]
r r r r
Doc ID 018940 Rev 1
for a list of abbreviations used in register descriptions.
24 23 22
PLLON Res Res
rw
8 7 6
HSITRIM[4:0]
r rw rw
21 20 19 18
CSS HSE
Res Res
ON BYP
rw rw
5 4 3 2
Res
rw rw rw
RM0091
17 16
HSE HSE
RDY ON
r rw
1 0
HSI
HSION
RDY
r rw