Figure 212. 10-Bit Address Read Access With Head10R=1 - STMicroelectronics STM32F05 series Reference Manual

RM0091

Figure 212. 10-bit address read access with HEAD10R=1

S
Master transmitter
In the case of a write transfer, the TXIS flag is set after each byte transmission, after the 9th
SCL pulse when an ACK is received.
A TXIS event generates an interrupt if the TXIE bit is set in the I2Cx_CR1 register. The flag
is cleared when the I2Cx_TXDR register is written with the next data byte to be transmitted.
The number of TXIS events during the transfer corresponds to the value programmed in
NBYTES[7:0]. If the total number of data bytes to be sent is greater than 255, reload mode
must be selected by setting the RELOAD bit in the I2Cx_CR2 register. In this case, when
NBYTES data have been transferred, the TCR flag is set and the SCL line is stretched low
until NBYTES[7:0] is written to a non-zero value.
The TXIS flag is not set when a NACK is received.
●
When RELOAD=0 and NBYTES data have been transferred:
–
–
●
If a NACK is received: the TXIS flag is not set, and a STOP condition is automatically
sent after the NACK reception. the NACKF flag is set in the I2Cx_ISR register, and an
interrupt is generated if the NACKIE bit is set.
1 1 1 1 0 X X 0
Slave address Slave address
R/W A
1st 7 bits
Write
In automatic end mode (AUTOEND=1), a STOP is automatically sent.
In software end mode (AUTOEND=0), the TC flag is set and the SCL line is
stretched low in order to perform software actions:
A RESTART condition can be requested by setting the START bit in the I2Cx_CR2
register with the proper slave address configuration, and number of bytes to be
transferred. Setting the START bit clears the TC flag and the START condition is
sent on the bus.
A STOP condition can be requested by setting the STOP bit in the I2Cx_CR2
register. Setting the STOP bit clears the TC flag and the STOP condition is sent on
the bus.
Doc ID 018940 Rev 1
Inter-integrated circuit (I
A DATA A
2nd byte
1 1 1 1 0 X X
Slave address
Sr R/W
1st 7 bits
DATA A/A
1
A DATA A DATA
Read
2
C) interface
A P
MS19822V1
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