I 2 C Interrupts; Table 75. I2C Interrupt Requests - STMicroelectronics STM32F05 series Reference Manual

RM0091
2
23.5 I C interrupts
The table below gives the list of I
Table 75.
Receive buffer not empty
Transmit buffer interrupt status
Stop detection interrupt flag
Transfer Complete Reload
Transfer complete
Address matched
NACK reception
Bus error
Arbitration loss
Overrun/Underrun
PEC error
Timeout/t
SMBus Alert
Depending on the product implementation, all these interrupts events can either share the
same interrupt vector (I2C global interrupt), or be grouped into 2 interrupt vectors (I2C event
interrupt and I2C error interrupt). Refer to the Vector table in the Interrupts and events
section for details.
In order to enable the I2C interrupts, the following sequence is required:
1. Configure and enable the I2C IRQ channel in the NVIC.
2. Configure the I2C to generate interrupts.
The I2C wakeup event is connected to the EXTI controller (refer to the External and internal
interrupt/event line mapping section).
2
I C Interrupt requests
Interrupt event
error
LOW
Doc ID 018940 Rev 1
Inter-integrated circuit (I
2
C interrupt requests.
Event flag/Interrupt
Event flag
RXNE
TXIS
STOPF
Write I2Cx_CR2 with
TCR
TC
ADDR
NACKF
BERR
ARLO
OVR
PECERR Write PECERRCF=1
TIMEOUT Write TIMEOUTCF=1
ALERT
Interrupt enable
clearing method
Read I2Cx_RXDR
register
Write I2Cx_TXDR
register
Write STOPCF=1
≠
NBYTES[7:0] 0
Write START=1 or
STOP=1
Write ADDRCF=1
Write NACKCF=1
Write BERRCF=1
Write ARLOCF=1
Write OVRCF=1
Write ALERTCF=1
2
C) interface
control bit
RXIE
TXIE
STOPIE
TCIE
ADDRIE
NACKIE
ERRIE
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