Syscfg Register Maps; Table 22. Syscfg Register Map And Reset Values - STMicroelectronics STM32F05 series Reference Manual

System configuration controller (SYSCFG)
Bits 31:9 Reserved, must be kept at reset value
9.1.7

SYSCFG register maps

The following table gives the SYSCFG register map and the reset values.
Table 22. SYSCFG register map and reset values
Offset Register
SYSCFG_CFGR1
0x00
Reset value
SYSCFG_EXTICR1
0x08
Reset value
SYSCFG_EXTICR2
0x0C
Reset value
SYSCFG_EXTICR3
0x10
Reset value
140/742
Bit 8 SRAM_PEF: SRAM parity flag
This bit is set by hardware when an SRAM parity error is detected. It is cleared
by software by writing '1'.
0: No SRAM parity error detected
1: SRAM parity error detected
Bits 7:3 Reserved, must be kept at reset value
Bit 2 PVD_LOCK: PVD lock enable bit
This bit is set by software and cleared by a system reset. It can be used to
enable and lock the PVD connection to TIM1/15/16/17 Break input, as well as
the PVDE and PLS[2:0] in the PWR_CR register.
0: PVD interrupt disconnected from TIM1/15/16/17 Break input. PVDE and
PLS[2:0] bits can be programmed by the application.
1: PVD interrupt connected to TIM1/15/16/17 Break input, PVDE and PLS[2:0]
bits are read only.
Bit 1 SRAM_PARITY_LOCK: SRAM parity lock bit
This bit is set by software and cleared by a system reset. It can be used to
enable and lock the SRAM parity error signal connection to TIM1/15/16/17 Break
input.
0: SRAM parity error disconnected from TIM1/15/16/17 Break input
1: SRAM parity error connected to TIM1/15/16/17 Break input
Bit 0 LOCKUP_LOCK: Cortex-M0 LOCKUP bit enable bit
This bit is set by software and cleared by a system reset. It can be use to enable
and lock the connection of Cortex-M0 LOCKUP (Hardfault) output to
TIM1/15/16/17 Break input.
0: Cortex-M0 LOCKUP output disconnected from TIM1/15/16/17 Break input
1: Cortex-M0 LOCKUP output connected to TIM1/15/16/17 Break input
Doc ID 018940 Rev 1
rw rw rw rw rw rw rw rw rw
EXTI3[3:0]
0 0 0 0 0
EXTI7[3:0]
0 0 0 0 0
EXTI11[3:0] EXTI10[3:0]
0 0 0 0 0
RM0091
EXTI2[3:0] EXTI1[3:0] EXTI0[3:0]
0 0 0 0 0 0 0 0
EXTI6[3:0] EXTI5[3:0] EXTI4[3:0]
0 0 0 0 0 0 0 0
EXTI9[3:0] EXTI8[3:0]
0 0 0 0 0 0 0 0
X X
0 0 0
0 0 0
0 0 0