Transmit Data Register (Usart_Tdr) - STMicroelectronics STM32F05 series Reference Manual

Universal synchronous asynchronous receiver transmitter (USART)
25.7.11

Transmit data register (USART_TDR)

Address offset: 0x28
Reset value: Undefined
31 30 29
Res Res Res
15 14 13
Res Res Res
Bits 31:9 Reserved, must be kept at reset value.
Bits 8:0 TDR[8:0]: Transmit data value
Note: This register must be written only when TXE=1.
632/742
28 27 26 25
Res Res Res Res
12 11 10 9
Res Res Res Res
Contains the data character to be transmitted.
The TDR register provides the parallel interface between the internal bus and the output
shift register (see Figure
When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the
value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because
it is replaced by the parity.
Doc ID 018940 Rev 1
24 23 22
Res Res Res
8 7 6
rw rw rw
228).
21 20 19 18
Res Res Res Res
5 4 3 2
TDR[8:0]
rw rw rw rw
RM0091
17 16
Res Res
1 0
rw rw