Interrupt Clear Register (I2Cx_Icr) - STMicroelectronics STM32F05 series Reference Manual

RM0091
23.7.8

Interrupt clear register (I2Cx_ICR)

Address offset: 0x1C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
ALERT
Res. Res.
CF OUTCF
w
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 ALERTCF: Alert flag clear
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
Bit 12 TIMOUTCF: Timeout detection flag clear
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
Bit 11 PECCF: PEC Error flag clear
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
Bit 10 OVRCF: Overrun/Underrun flag clear
Bit 9 ARLOCF: Arbitration Lost flag clear
Bit 8 BERRCF: Bus error flag clear
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 STOPCF: Stop detection flag clear
Bit 4 NACKCF: Not Acknowledge flag clear
Bit 3 ADDRCF: Address Matched flag clear
Bits 2:0 Reserved, must be kept at reset value.
28 27 26 25
Res. Res. Res.
12 11 10 9
TIM ARLO
PECCF OVRCF
CF
w w w w
Writing 1 to this bit clears the ALERT flag in the I2Cx_ISR register.
Please refer to Section 23.3: I2C
Writing 1 to this bit clears the TIMEOUT flag in the I2Cx_ISR register.
Please refer to Section 23.3: I2C
Writing 1 to this bit clears the PECERR flag in the I2Cx_ISR register.
Please refer to Section 23.3: I2C
Writing 1 to this bit clears the OVR flag in the I2Cx_ISR register.
Writing 1 to this bit clears the ARLO flag in the I2Cx_ISR register.
Writing 1 to this bit clears the BERRF flag in the I2Cx_ISR register.
Writing 1 to this bit clears the STOPF flag in the I2Cx_ISR register.
Writing 1 to this bit clears the ACKF flag in I2Cx_ISR register.
Writing 1 to this bit clears the ADDR flag in the I2Cx_ISR register. Writing 1 to this bit also
clears the START bit in the I2Cx_CR2 register.
Doc ID 018940 Rev 1
Inter-integrated circuit (I
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
BERR STOP
Res. Res.
CF CF
w w
implementation.
implementation.
implementation.
2
C) interface
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
NACK ADDR
Res. Res.
CF CF
w w
16
Res.
0
Res.
531/742