Tim2 And Tim3 Slave Mode Control Register; Tim3_Smcr) - STMicroelectronics STM32F05 series Reference Manual

General-purpose timers (TIM2 and TIM3)
16.4.3 TIM2 and TIM3 slave mode control register (TIM2_SMCR and

TIM3_SMCR)

Address offset: 0x08
Reset value: 0x0000
15 14 13
ETP ECE ETPS[1:0]
rw rw rw
Bit 15 ETP: External trigger polarity
Bit 14 ECE: External clock enable
Bits 13:12 ETPS: External trigger prescaler
332/742
12 11 10 9
ETF[3:0]
rw rw rw rw
This bit selects whether ETR or ETR is used for trigger operations
0: ETR is noninverted, active at high level or rising edge
1: ETR is inverted, active at low level or falling edge
This bit enables External clock mode 2.
0: External clock mode 2 disabled
1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF
signal.
1: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI
connected to ETRF (SMS=111 and TS=111).
2: It is possible to simultaneously use external clock mode 2 with the following slave modes:
reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to
ETRF in this case (TS bits must not be 111).
3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the
external clock input is ETRF.
External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A
prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external
clocks.
00: Prescaler OFF
01: ETRP frequency divided by 2
10: ETRP frequency divided by 4
11: ETRP frequency divided by 8
Doc ID 018940 Rev 1
8 7 6 5
MSM TS[2:0]
rw rw rw rw
4 3 2 1
Res. SMS[2:0]
rw rw rw
RM0091
0
rw