Table of Contents
Advertisement
RM0091
27.6.2
TSC interrupt enable register (TSC_IER)
Address offset: 0x04
Power-on reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 MCEIE: Max count error interrupt enable
Bit 0 EOAIE: End of acquisition interrupt enable
27.6.3
TSC interrupt clear register (TSC_ICR)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 MCEIC: Max count error interrupt clear
Bit 0 EOAIC: End of acquisition interrupt clear
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
This bit is set and cleared by software to enable/disable the max count error interrupt.
0: Max count error interrupt disabled
1: Max count error interrupt enabled
This bit is set and cleared by software to enable/disable the end of acquisition interrupt.
0: End of acquisition interrupt disabled
1: End of acquisition interrupt enabled
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
This bit is set by software to clear the max count error flag and it is cleared by hardware
when the flag is reset. Writing a '0' has no effect.
0: No effect
1: Clears the corresponding MCEF of the TSC_ISR register
This bit is set by software to clear the end of acquisition flag and it is cleared by hardware
when the flag is reset. Writing a '0' has no effect.
0: No effect
1: Clears the corresponding EOAF of the TSC_ISR register
Doc ID 018940 Rev 1
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
Res.
Res.
Res.
Res.
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
Res.
Res.
Res.
Res.
Touch sensing controller (TSC)
20
19
18
Res.
Res.
Res.
4
3
2
Res.
Res.
Res.
MCEIE EOAIE
20
19
18
Res.
Res.
Res.
4
3
2
Res.
Res.
Res.
17
16
Res.
Res.
1
0
rw
rw
17
16
Res.
Res.
1
0
MCEIC EOAIC
rw
rw
693/742
Advertisement
Table of Contents
Need help?
Do you have a question about the STM32F05 series and is the answer not in the manual?
Questions and answers