Figure 245. Irda Sir Endec- Block Diagram; Figure 246. Irda Data Modulation (3/16) -Normal Mode - STMicroelectronics STM32F05 series Reference Manual

RM0091
IrDA low-power mode
Transmitter:
In low-power mode the pulse width is not maintained at 3/16 of the bit period. Instead, the
width of the pulse is 3 times the low-power baud rate which can be a minimum of 1.42 MHz.
Generally, this value is 1.8432 MHz (1.42 MHz < PSC< 2.12 MHz). A low-power mode
programmable divisor divides the system clock to achieve this value.
Receiver:
Receiving in low-power mode is similar to receiving in normal mode. For glitch detection the
USART should discard pulses of duration shorter than 1/PSC. A valid low is accepted only if
its duration is greater than 2 periods of the IrDA low-power Baud clock (PSC value in the
USART_GTPR register).
Note: A pulse of width less than two and greater than one PSC period(s) may or may not be
rejected.
The receiver set up time should be managed by software. The IrDA physical layer
specification specifies a minimum of 10 ms delay between transmission and reception (IrDA
is a half duplex protocol).

Figure 245. IrDA SIR ENDEC- block diagram

Figure 246. IrDA data modulation (3/16) -Normal Mode

TX
IrDA_OUT
IrDA_IN
RX
Universal synchronous asynchronous receiver transmitter (USART)
TX
SIREN
USART
RX
Start
bit
0
0
1
bit period
0
1
0
Doc ID 018940 Rev 1
SIR
Transmit
Encoder
SIR
Receive
Decoder
0
0
1
0
0
1
USART_TX
OR
IrDA_OUT
IrDA_IN
USART_RX
stop bit
0
1 1
1
3/16
0
1
1
1
603/742