STMicroelectronics STM32F05 series Reference Manual page 529

RM0091
Bit 10 OVR: Overrun/Underrun (slave mode)
Note: This bit is cleared by hardware when PE=0 or SWRST is set.
Bit 9 ARLO: Arbitration lost
Note: This bit is cleared by hardware when PE=0 or SWRST is set.
Bit 8 BERR: Bus error
Note: This bit is cleared by hardware when PE=0 or SWRST is set.
Bits 7 TCR: Transfer Complete Reload
Note: This bit is cleared by hardware when PE=0 or SWRST is set.
Bit 6 TC: Transfer Complete (master mode)
Note: This bit is cleared by hardware when PE=0 or SWRST is set.
Bit 5 STOPF: Stop detection flag
– either as a master, provided that the STOP condition is generated by the peripheral.
– or as a slave, provided that the peripheral has been addressed previously during this
Note: This bit is cleared by hardware when PE=0 or SWRST is set.
Bit 4 NACKF: Not Acknowledge received flag
Note: This bit is cleared by hardware when PE=0 or SWRST is set.
Bit 3 ADDR: Address matched (slave mode)
Note: This bit is cleared by hardware when PE=0 or SWRST is set.
This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun
error occurs. It is cleared by software by setting the OVRCF bit.
This flag is set by hardware when the interface in case of arbitration loss. It is cleared by
software by setting the ARLOCF bit.
This flag is set by hardware when a misplaced Start or Stop condition is detected. It is
cleared by software by setting BERRCF bit.
This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is
cleared by software when NBYTES is written to a non-zero value.
This flag is only for master mode, or for slave mode when the SBC bit is set.
This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been
transferred. It is cleared by software when START bit or STOP bit is set.
This flag is set by hardware when a Stop condition is detected on the bus and the peripheral
is involved in this transfer:
transfer.
It is cleared by software by setting the STOPCF bit.
This flag is set by hardware when a NACK is received after a byte transmission. It is cleared
by software by setting the NACKCF bit.
This bit is set by hardware as soon as the received slave address matched with one of the
enabled slave addresses. It is cleared by software by setting ADDRCF bit.
Doc ID 018940 Rev 1
Inter-integrated circuit (I
2
C) interface
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