Cec Configuration Register (Cec_Cfgr) - STMicroelectronics STM32F05 series Reference Manual

RM0091
28.7.2

CEC configuration register (CEC_CFGR)

This register is used to configure the HDMI-CEC controller.
Address offset: 0x04
Reset value: 0x0000 0000
Caution: It is mandatory to write CEC_CFGR only when CECEN=0
31 30 29
LSTN
rw
15 14 13
Res. Res. Res. Res.
Reserved, must be kept at reset value.
Bit 31 LSTN: Listen mode
LSTN bit is set and cleared by software.
0: CEC peripheral receives only message addressed to its own address (OAR). Messages
addressed to different destination are ignored. Broadcast messages are always received.
1: CEC peripheral receives messages addressed to its own address (OAR) with positive acknowledge.
Messages addressed to different destination are received, but without interfering with the CEC bus: no
acknowledge sent.
Bits 30:16 OAR: Own Address
OAR bits are set by software to configure the own address of the CEC device. It is used in receive
mode only. At the end of HEADER reception OAR is compared with received destination address. In
case of matching address message is received. In case of not-matching address message is received
only in listen mode (LSTN=1), but without acknowledge sent. Broadcast messages are always
received.
This register can handle multiple OAR, a logic 1 value on each bit of this reg corresponds to the CEC
address identified by the bit position.
Example:
OAR = 00000000100001 means that CEC has as address 0x0 and 0x5. Consequently, each message
directed to one of these addresses is received.
Note: It is possible to configure OAR=0xF: in this case only broadcast messages are received if
LSTN=0, while all messages are received and never acknowledged if LSTN=1.
Bits 15:9 Reserved, must be kept at reset value.
Bit 8 SFTOP: SFT Option Bit
The SFTOPT bit is set and cleared by software.
0: SFT timer starts when TXSOM is set by software
1: SFT timer starts automatically at the end of message transmission/reception.
Bit 7 BRDNOGEN: Avoid Error-Bit Generation in Broadcast
The BRDNOGEN bit is set and cleared by software.
0: BRE detection with BRESTP=1 and BREGEN=0 on a broadcast message generates an Error-Bit
on the CEC line. LBPE detection with LBPEGEN=0 on a broadcast message generates an Error-Bit
on the CEC line
1: Error-Bit is not generated in the same condition as above. An Error-Bit is not generated even in
case of an SBPE detection in a broadcast message if listen mode is set.
28 27 26 25
12 11 10 9
Res. Res. Res.
Doc ID 018940 Rev 1
HDMI-CEC controller (HDMI-CEC)
24 23 22 21
OAR[14:0]
rw
8 7 6 5
SFT LBPE BRE
BRDN
OGEN
OPT GEN GEN
rw rw rw rw
20 19 18 17
4 3 2 1
BRE RX
SFT[2:0]
STP TOL
rw rw rw
16
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