Tim15 Status Register (Tim15_Sr) - STMicroelectronics STM32F05 series Reference Manual

RM0091
18.5.5

TIM15 status register (TIM15_SR)

Address offset: 0x10
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:11
Bit 10 CC2OF: Capture/Compare 2 overcapture flag
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
Bit 8
Bit 7 BIF: Break interrupt flag
Bit 6 TIF: Trigger interrupt flag
Bit 5 COMIF: COM interrupt flag
Bits 5:3
Bit 2 CC2IF: Capture/Compare 2 interrupt flag
12 11 10 9
Res. CC2OF CC1OF
rc_w0 rc_w0
Reserved, always read as 0.
refer to CC1OF description
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to '0'.
0: No overcapture has been detected
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Reserved, always read as 0.
This flag is set by hardware as soon as the break input goes active. It can be cleared by
software if the break input is not active.
0: No break event occurred
1: An active level has been detected on the break input
This flag is set by hardware on trigger event (active edge detected on TRGI input when the
slave mode controller is enabled in all modes but gated mode, both edges in case gated
mode is selected). It is cleared by software.
0: No trigger event occurred
1: Trigger interrupt pending
This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE,
CCxNE, OCxM– have been updated). It is cleared by software.
0: No COM event occurred
1: COM interrupt pending
Reserved, always read as 0.
refer to CC1IF description
Doc ID 018940 Rev 1
General-purpose timers (TIM15/16/17)
8 7 6 5
Res. BIF TIF COMIF
rc_w0 rc_w0
4 3 2 1
Res. Res. CC2IF CC1IF
rc_w0 rc_w0
0
UIF
rc_w0
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